The invention relates to an integrated circuit having a phase-locked loop.
Delay-Locked Loops (DLLs) are integrated circuits having a phase-locked loop in which an output clock signal is generated with a specific phase shift relative to an input clock signal. DLLs usually have a delay unit which is arranged between a clock input and a clock output and whose delay time is adjustable. The clock input for the input clock signal and the clock output for the output clock signal are connected to a phase comparator or phase detector. A phase regulator connected downstream of the phase detector generates a control signal which is used to set the delay time of the delay unit. The generation and updating of the control signal by the phase regulator are in this case often effected synchronously with a control clock signal.
Since edges of the output clock signal are critical for the driving of circuit units connected downstream of the DLL, it is desirable for these edges to be generated as far as possible without any disturbances. However, it can happen that the phase regulator clocked by the control signal performs adaptation or updating of the control signal fed to the delay unit shortly before or even during the occurrence of an edge of the output clock signal. This leads to the edges of the output clock signal being disturbingly influenced in an undesirable manner. The disturbance can be attributed to the fact that when there is a change in the control signal, a change is made to the delay time of the delay unit for which specific switching operations have to be carried out within the delay unit.
The invention is based on the object of specifying an integrated circuit of the type described in the introduction which avoids disturbances of the edges of the output clock signal on account of the updating of the control signal generated by the phase regulator.
This object is achieved by means of an integrated circuit in accordance with patent claim 1. The dependent claims relate to advantageous designs and developments of the invention.
According to the invention, updating of the control signal fed to the control input of the delay unit is triggered by an edge of the output clock signal occurring at the clock output.
By virtue of the fact that the updating of the control signal is triggered only by the edge of the output clock signal, it is no longer possible for the edge to be disturbingly influenced by the setting operations caused by the updating within the delay unit.
It has been customary hitherto for the phase regulator to be driven by a control clock signal which is independent of the output clock signal of the phase-locked loop. As a result, the control signal fed to the delay unit was updated independently of the output clock signal, so that the edges of the output clock signal could be disturbingly influenced.
According to a first embodiment of the invention, the dependence of the updating of the control signal on the output clock signal is achieved by the phase regulator being clocked by the output clock signal and not by a control clock signal independent thereof. For this purpose, a clock input of the phase regulator is connected to the clock output of the delay unit. The phase regulator then generates the updated values of the control signal in a manner dependent on the edges of the output clock signal.
According to another embodiment of the invention, the integrated circuit has a first transfer unit, which is arranged between the output of the phase regulator and the control input of the first delay unit and whose clock input is connected to the clock output of the first delay unit. The first transfer unit forwards the control signal fed to it by the phase regulator to the first delay unit in a manner dependent on the edge of the first output clock signal, which is fed to its clock input.
In this embodiment, it is possible for the phase regulator to be clocked by a control clock signal which remains independent of the output clock signal of the first delay unit. The first transfer unit, which may be, for example, a clocked holding circuit (latch), nevertheless ensures that the respective updated value of the control signal is forwarded to the control input of the first delay unit only after the occurrence of an edge of the output clock signal. Therefore, undesirable disturbances of edges of the output clock signal on account of alterations to the control signal generated by the phase regulator are avoided in this way as well.
According to one development of the invention, the integrated circuit has a second delay unit having a clock input for feeding in a second input clock signal, having a clock output for outputting a second output clock signal, which is delayed with respect to the second input clock signal, and having at least one control input for setting its delay time. The circuit further has a second transfer unit, via which the output of the phase regulator is connected to the control input of the second delay unit, which has a clock input connected to the clock output of the second delay unit, and which forwards the control signal fed to it by the phase regulator to the second delay unit in a manner dependent on the edge of the second output clock signal, which is fed to its control input.
In this development of the invention, therefore, the phase regulator serves both for regulating the phase shift of the first output clock signal with respect to the first input clock signal and for controlling the phase shift of the second output clock signal with respect to the second input clock signal. This development is particularly suitable for first and second input clock signals which are such that they have the same frequency and have a specific phase shift relative to one another. The second transfer unit ensures that the edges of the second output clock signal are also not disturbingly influenced by the updating of the control signal which is fed both to the first and to the second delay unit.
According to a further development of the invention, the first delay unit has a series circuit formed by a first delay stage and a second delay stage. The phase regulator serves for generating a control signal for the first delay stage and a control signal for the second delay stage. The phase regulator is connected to the first delay stage via a second transfer unit and to the second delay stage via a series circuit formed by a third transfer unit and the first transfer unit. Clock inputs of the second and third transfer units are connected to a clock output of the first delay stage.
The second and third transfer units ensure that the control signals which are generated at the same instant by the phase regulator are fed to the two delay stages during a period of the output clock signal. The second transfer unit prevents a disturbance of the edges of the output clock signal of the first delay stage and the first transfer unit prevents a disturbance of the edges of the output clock signal of the second delay stage by the updating of the respective control signal.
By way of example, the first delay stage may serve for the course setting of a delay time and the second delay stage may serve for the fine setting of a delay time of the first delay unit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a phase-locked loop, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.